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DS26502DK
FPGA Control Registers
The FPGA register set consists of two types of registers: level setting and clock multiplexing. There are 10 registers
for tri-state and level-control setting when in hardware mode. The level-setting registers are only valid when the
DS26502 is in hardware mode (BIS1:0 = 11). When in nonhardware mode, the FPGA pins affected by the level
registers are automatically either tri-stated, or assume an alternate function (e.g., they function as address databus
pins or SPI pins). Exceptions are given with the register descriptions.
Register Name: LEVEL1
Register Description: DS26502 Pin Settings (THZE, BTS, BIS1, BIS0)
Register Offset: 0x0011
Bit #
Name
Default
7
THZEtri
0
6
THZE_Lev
0
5
BTStri
0
4
BTS_Lev
0
3
BIS1tri
0
2
BIS1_Lev
0
1
BIS0tri
0
0
BIS0_Lev
1
Note: This register is only valid in ALL modes (many of the level registers are only valid in hardware mode).
Bits 7 and 6: DS26502 THZE Tri-State and Level (THZEtri and THZE_Lev)
00 = FPGA drives THZE with 0V
01 = FPGA drives THZE with 3.3V
1x = FPGA tri-states THZE pin
Bit 5 and 4: DS26502 BTS Tri-State and Level (BTStri and BTS_Lev)
00 = FPGA drives BTS with 0V
01 = FPGA drives BTS with 3.3V
1x = FPGA tri-states BTS pin
Bits 3 and 2: DS26502 BIS1 Tri-State and Level (BIS1tri and BIS1_Lev)
00 = FPGA drives BIS1 with 0V
01 = FPGA drives BIS1 with 3.3V
1x = FPGA tri-states BIS1 pin
Bits 1 and 0: DS26502 BIS0 Tri-State and Level (BIS0tri and BIS0_Lev)
00 = FPGA drives BIS0 with 0V
01 = FPGA drives BIS0 with 3.3V
1x = FPGA tri-states BIS0 pin
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